SIPS 2009: Program
SESSION
October 7, 2009
9:00AM - 9:15AM Pieni Sali
Opening
SESSION KEY1
October 7, 2009
9:15AM - 10:00AM Pieni Sali
Keynote
Chair: Markku Renfors, Tampere University of Technology
9:15 AM
Signal Processing Implementation Challenges in Mobile Terminals
Henry Tirri, Nokia Research Center, Palo Alto, CA, USA
SESSION
October 7, 2009
10:00AM - 11:00AM Rondo
SoC Industry Track, SoC Poster Session, Exhibition, Coffee Break
SESSION COM1
October 7, 2009
11:00AM - 12:20PM Sonaatti
DSP for Communications I
Chair: Jarmo Takala, Tampere University of Technology
11:00AM
Sparse Severe Error Removal in OFDM Demodulators for Erasure Channels
Renfei Liu and Keshab K. Parhi
University of Minnesota, Twin Cities, USA
11:20AM
A Novel Circulant Approximation Method for Frequency Domain LMMSE Equalization
Clemens Buchacher1, Joachim Wehinger1, Mario Huemer2
1Infineon Technologies AG, Germany, 2Klagenfurt University, Austria
11:40AM
Multi-Level Modulation Soft-Decision Demapper for DVB-S2
Jang Woong Park1, Myung Hoon Sunwoo1, Pan Soo Kim2, Dae-Ig Chang2
1Ajou Univ., South Korea, 2ETRI, South Korea
12:00PM
Design of Rotated QAM Mapper/Demapper for the DVB-T2 Standard
Meng Li, Charbel Abdel Nour, Christophe Jego, Catherine Douillard
Telecom Bretagne, France
SESSION
October 7, 2009
12:20PM - 1:20PM
Lunch
SESSION COM2
October 7, 2009
1:20PM - 2:40PM Sonaatti
DSP for Communications II
Chair: Warren Gross, McGill University
1:20PM
Register File Exploration for a Multi-standard Wireless Forward Error Correction ASIP
Praveen Raghavan and Francky Catthoor
IMEC vzw and KULeuven, Belgium
1:40PM
Implementation of the W-CDMA Cell Search on a MPSoC Designed for Software Defined Radios
Fabio Garzia1, Roberto Airoldi1, Tapani Ahonen1, Dragomir Milojevic2, Jari Nurmi1
1Tampere Univ. Tech., Finland, 2Université Libre de Bruxelles, Belgium
2:00PM
Two-Parallel Concatenated BCH Super-FEC Architecture for 100-Gb/s Optical Communications
Sangho Yoon1, Hanho Lee1, Kihoon Lee1, Chang-Seok Choi1, Jongyoon Shin2, Jongho Kim2, Je-Soo Ko2
1Inha University, South Korea, 2ETRI, South Korea
2:20PM
Low-Power Implementation of a High-Throughput LDPC Decoder for IEEE 802.11n Standard
Junho Cho1, Naresh Shanbhag2, Wonyong Sung1
1Seoul National University, South Korea, 2University of Illinois at Urbana-Champaign, USA
SESSION PSTR1
October 7, 2009
2:40PM - 3:40PM Rondo
Posters I
Low-Complexity Frame-Size Down-Scaling Integrated with IDCT
Meng-Lin Hsia and Oscal Tzyh-Chiang Chen
National Chung Cheng University, Taiwan
Is The Differential Frequency-Based Attack Effective Against Random Delay insertion?
Yingxi Lu1, Keanhong Boey1, Maire O'Neill1, John McCanny1, Akashi Satoh2
1Queen's University Belfast, UK, 2National Institute of Advanced Industrial Science and Technology, Japan
Approximating Sine Functions using Variable-Precision Taylor Polynomials
Claudio Brunelli, Heikki Berg, David Guevorkian
Nokia Research Center, Helsinki, Finland
Reducing Processor Energy Consumption by Compiler Optimization
Vladimír Guzma, Teemu Pitkänen, Pertti Kellomäki, Jarmo Takala
Tampere Univ. Tech., Finland
Hardware Reduction Methodology for 2-Dimensional Kurtotic Fast ICA Based on Algorithmic Analysis and Architectural Symmetry
Amit Acharyya, Koushik Maharatna, Bashir M. Al-Hashimi
University of Southampton, UK
Parallel Object Detection on Heterogeneous Multicore Platforms
Shin-Kai Chen, Tay-Jyi Lin, Chih-Wei Liu
National Chiao Tung University, Taiwan
Reconfigurable Video Decoder with Transform Acceleration
Lassi Nurmi, Perttu Salmela, Pertti Kellomäki, Pekka Jääskeläinen, Jarmo Takala
Tampere Univ. Tech., Finland
SIMD Processor Based Implementation of Recursive Filtering Equations
Jaewoo Ahn, Hoseok Chang, Junho Cho, Wonyong Sung
Seoul National University, Korea
SESSION VIDP
October 7, 2009
3:40PM - 5:00PM Sonaatti
Video Processing
Chair: Zhiyuan Yan, Lehigh University
3:40PM
An Adaptive Fast Multiple Reference Frame Selection Algorithm for H.264/AVC Using Reference Region Data
Kangjun Lee1, Gwanggi Jeon1, Rafael Falcon2, Changwoo Ha1, Jechang Jeong1
1Hanyang University, South Korea, 2University of Ottawa, Canada
4:00PM
A Early Block Type Decision Method for Intra Prediction in H.264/AVC
Jungho Do, Sangkwon Na, Chong-Min Kyung
KAIST, South Korea
4:20PM
Design of an Interlayer Deblocking Filter Architecture for H.264/SVC Based on a Novel Sample-Level Filtering Order
Guilherme Corrêa1, Thaísa Silva2, Luís A. Cruz3, Luciano Agostini1
1UFPel, Brazil, 2UFRGS, Brazil, 3University of Coimbra, Portugal
4:40PM
Fast Pipeline Schedule for an H.264 Intra Frame Encoder with Early Termination
Young-Joon Jo, Jin-Su Jung, Hyuk-Jae Lee
Seoul National University, South Korea
SESSION KEY2
October 7, 2009
5:00PM-5:45PM Pieni Sali
Keynote II
Chair: Wonyong Sung, Seoul National University
Being Globally Energy-Aware in DSP System Design
Chong-Min Kyung, Korea Advanced Institute of Science and Technology
SESSION KEY3
October 8, 2009
9:00AM - 9:45AM Studio
Keynote III
Chair: Jari Nurmi, Tampere University of Technology
Low-Power Solutions for Reconfigurable Computing
Steve Wilton, University of British Columbia, Vancouver, BC, Canada
SESSION
October 8, 2009
9:45AM - 10:00AM Rondo
Coffee Break
SESSION IMPL1
October 8, 2009
10:00AM - 11:20AM Studio
DSP Implementations I
Chair: Nam Ling, Santa Clara University
10:00AM
Architectural Support for the Orchestration of Fine-Grained Multiprocessing for Portable Streaming Applications
Jani Boutellier1, Alessandro Cevrero2, Philip Brisk2, Paolo Ienne2
1University of Oulu, Finland, 2École Polytechnique Fédérale de Lausanne, Switzerland
10:20AM
FPGA Architecture for 2D Fast Fourier Transform Based on 2D Decomposition for Large-Sized Data
Jung Sub Kim1, Chi-Li Yu2, Lanping Deng2, Srinidhi Kestur1, Vijaykrishnan Narayanan1, Chaitali Chakrabarti2
1Pennsylvania State University, USA, 2Arizona State University, USA
10:40AM
Rank Metric Decoder Architectures for Noncoherent Error Control in Random Network Coding
Ning Chen, Maximilien Gadouleau,, Zhiyuan Yan
Lehigh University, USA
SESSION DSGN
October 8, 2009
11:20AM - 12:20PM Studio
Design Methods and Tools
Chair: Chaitali Chakrabarti, Arizona State University
11:00AM
System Level DSP Synthesis Using Voltage Overscaling, Unequal Error Protection & Adaptive Quality Tuning
Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy
Purdue University, USA
11:20AM
Loop Scheduling with Memory Access Reduction under Register Constraints for DSP Applications
Meng Wang and Zili Shao
The HK Polytechnic University
11:40AM
Interface-Based Hierarchy for Synchronous Data-Flow Graphs
Jonathan Piat1, Shuvra Bhattacharyya2, Mickaël Raulet1
1IETR/INSA, Rennes, France, 2Univ. Maryland, College Park, MD, USA
12:00PM
Power-aware Evaluation Flow for Digital Decimation Filter Architectures for High-Speed ADCs
David Novo, Robert Fasthuber, Praveen Raghavan, Andre Bourdoux, Min Li, Liesbet Van der Perre, Francky Catthoor
IMEC and KULeuven, Belgium
SESSION
October 8, 2009
12:20PM - 1:20PM
Lunch
SESSION IMPL2
October 8, 2009
1:20PM - 2:40PM Studio
DSP Implementations II
Chair: Shuvra Bhattacharyya, University of Maryland, College Park
1:20PM
Locally Adaptive Speckle Noise Reduction Using Maximum A Posteriori Estimation Based on Maxwell Distribution
Sung Gug Kim, Yoo Shin Kim, Il Kyu Eom
Pusan National University, South Korea
1:40PM
Hybridkernel: Preemptive Kernel with Event-Driven Extension for Resource Constrained Wireless Sensor Networks
Teemu Laukkarinen, Ville A. Kaseva, Jukka Suhonen, Timo D. Hämäläinen, Marko Hännikäinen
Tampere Univ. Tech., Finland
2:00PM
Morphable DPU: Smart and Efficient Data Path for Signal Processing Applications
Muhammad Ali Shami and Ahmed Hemani
Royal Institute of Technology, Sweden
2:20PM
Configurable High-Performance Video Platform Using Multiple RISC Clusters Connected with Separated Data and Control Networks
Daewoong Kim, Kilhyung Cha, Soonwoo Choi, Soo-Ik Chae
Seoul National University, South Korea
SESSION PSTR2
October 8, 2009
2:40PM - 3:40PM Rondo
Posters II
High-Speed Area-Efficient Versatile Reed-Solomon Decoder Design for Multi-Mode Applications
Bo Yuan1, Li Li1, Zhongfeng Wang2
1Nanjing University, P.R. China, 2Broadcom Corporation, USA
Low-Power Pre-Decoding Based Viterbi Decoder for Tail-Biting Convolutional Codes
Rami Abdallah1, Seok-Jun Lee2, Manish Goel2, Naresh Shanbhag1
1University of Illinois at Urbana Champaign, USA, 2Texas Instruments, Dallas, TX, USA
CAC CODEC Designs Based on Numeral Systems
Xuebin Wu and Zhiyuan Yan
Lehigh University, USA
Robust Tree Construction and Maintenance for Global Time Synchronization Protocols in Wireless Sensor Networks
Ville Kaseva, Timo Hämäläinen, Marko Hännikäinen
Tampere Univ. Tech., Finland
A New FPGA-Based Postprocessor Architecture for Channel Mismatch Correction of Time Interleaved ADCs
Asgar Abbaszadeh1 and Khosrov Dabbagh-Sadeghipour2
1East Azerbaijan Science and Technology Park, Iran, 2University of Tabriz, Iran
Rectangular Constellation-Based Blind Equalization with Recursive Least-Squares Algorithm
Juuso Alhava and Markku Renfors
Tampere Univ. Tech., Finland
An Ultra Low-Power VAD Hardware Implementation for Intelligent Ubiquitous Sensor Networks
Hiroki Noguchi, Tomoya Takagi, Masahiko Yoshimoto, Hiroshi Kawaguchi
Kobe University, Japan
A RAIM Approach to GNSS Outlier and Cycle Slip Detection Using L1 Carrier Phase Time-Differences
Martti Kirkko-Jaakkola1, Johannes Traugott2, Dennis Odijk3, Jussi Collin1, Gottfried Sachs2, Florian Holzapfel2
1Tampere Univ. Tech., Finland, 2Technische Universität München, Germany, 3Curtin University of Technology, Australia
SESSION COM3
October 8, 2009
3:40PM - 5:00PM Studio
DSP for Communications III
Chair: Jari Nurmi, Tampere University of Technology
3:40PM
Conflict Resolution for Pipelined Layered LDPC Decoders
Cédric Marchand1, Jean-Baptiste Doré2, Laura Conde-Canencia1, Emmanuel Boutillon1
1Université Européenne de Bretagne, Lorient, France, 2NXP Semiconductors, Colombelles, France
4:00PM
A Channel-Adaptive Early Termination Strategy for LDPC Decoders
Yu-Hsin Chen, Yi-Ju Chen, Xin-Yu Shih, An-Yeu Wu
National Taiwan University, Taiwan
4:20PM
Bidirectional Interleavers for LDPC Decoders Using Transmission Gates
Kevin Cushon, Warren Gross, Shie Mannor
McGill University, Canada
4:40PM
An Improved Min-Sum Based Column-Layered Decoding Algorithm for LDPC Codes
Lin Jun1, Sha Jin1, Wang Zhongfeng2, Li Li1
1Nanjing University, P.R. China, 2Broadcom Corporation, USA
SESSION KEY4
October 9, 2009
9:00AM - 9:45AM Studio
Keynote IV
Chair: Jarmo Takala, Tampere University of Technology
Model-Based Design for Signal Processing Systems
Edward A. Lee, University of California at Berkeley, USA
SESSION
October 9, 2009
9:45AM - 10:00AM
Coffee Break
SESSION IMGP
October 9, 2009
10:00AM - 11:00AM Studio
Image Processing
Chair: Leonel Sousa, Technical University of Lisbon
10:00AM
A Novel Trace-Pipelined Binary Arithmetic Coder Architecture for JPEG2000
Min-Soo Rhu and In-Cheol Park
Korea Advanced Institute of Science and Technology (KAIST), South Korea
10:20AM
Software Designs of Image Processing Tasks with Incremental Refinement of Computation
Davide Anastasia and Yiannis Andreopoulos
University College London, UK
10:40AM
Memory Access Characteristics of H.264 Video Encoder on Embedded Processor
Eero Aho1, Kimmo Kuusilinna1, Jari Nikara2
1Nokia Research Center, Tampere, Finland, 2Nokia Research Center, Berkeley, CA, USA
SESSION GNSS
October 9, 2009
11:00AM - 11:40AM Studio
Special Session: DSP in GNSS
Chair: John Raquet, Air Force Institute of Technology
Co-Chair: Jussi Collin, Tampere University of Technology
11:00AM
Optimal Dual Frequency Combination for Galileo Mass Market Receiver Baseband
Heikki Hurskainen1, Elena-Simona Lohan1, Jari Nurmi1, Stephan Sand2, Christian Mensing2, Marco Detratti3
1Tampere Univ. Tech., Finland, 2German Aerospace Center, Germany, 3Acorde Technologies S.A., Spain
11:20AM
Enhancing GNSS Signal Acquisition through the Gradient Method
Antonio Cavaleri1, Letizia Lo Presti1, Marco Pini2
1Politecnico di Torino, Italy, 2Istituto Superiore Mario Boella, Italy
SESSION GPU1
October 9, 2009
11:40AM - 12:20PM Studio
Special Session: DSP on GPUs
Chair: Wonyong Sung, Seoul National University
11:40AM
OpenCL Embedded Profile Prototype in Mobile Device
Jyrki Leskelä, Mika Salmela, Jarmo Nikula
Nokia Corp., Finland
12:00PM
Massively Parallel Implementation of Cyclic LDPC Codes on a General Purpose Graphics Processing Unit
Hyunwoo Ji, Junho Cho, Wonyong Sung
Seoul National University, South Korea
SESSION
October 9, 2009
12:20PM - 1:20PM
Lunch
SESSION GPU2
October 9, 2009
1:20PM - 2:40PM Studio
Special Session: DSP on GPUs
Chair: Wonyong Sung, Seoul National University
1:20PM
Development and Evaluation of Scalable Video Motion Estimators on GPU
Svetislav Momcilovic and Leonel Sousa
INESC-ID/TU Lisbon, Portugal
1:40PM
Real-time Motion Estimation for 1080p Videos on Graphics Processing Units with Shared Memory Optimization
Shang-Te Yang, Tsung-Kai Lin, Shao-Yi Chien
National Taiwan University, Taiwan
2:00PM
A GPU Implementation of A Real-Time MIMO Detector
Michael Wu, Yang Sun, Siddharth Gupta, Joseph R. Cavallaro
Rice University, USA
2:20PM
Processing of Synthetic Aperture Radar Data with GPGPU
Carmine Clemente, Maurizio di Bisceglie, Michele Di Santo, Nadia Ranaldo, Marcello Spinelli
Università degli Studi del Sannio, Italy
SESSION
October 9, 2009
2:40PM - 3:00PM Studio
Closing