This paper presents a low complexity soft-decision demapper for the Digital Video Broadcasting – Satellite second generation (DVB-S2). To achieve a good Bit Error Rate (BER) performance of a Low Density Parity Check (LDPC) code decoder, the received signal should be soft-decided rather than hard-decided. However, the soft-decision demapper requires high hardware complexity to support higher-order modulation modes. The proposed soft-decision demapper can reduce the hardware complexity by reusing multipliers. In addition, we propose an efficient soft-decision demapper interface that can operate at a symbol rate and we can replace a Parallel to Serial (P/S) converter with the proposed interface by locating between an M-Phase Shift Keying (PSK) demodulator and the proposed demapper. The proposed soft-decision demapper and and its interface have been verified in XilinxTM Virtex II.