In this paper we proposed a hardware reduction methodology through detailed algorithmic analysis and exploiting datapath symmetry for 2-D Kurtotic Fast ICA. The relationship of the hardware saving with respect to input data frame-length and maximum iteration for convergence is also explored. An example architecture following the developed hardware reduction methodology consumes 3.55 mm2 silicon area and 27.1 μW at 1 MHz @1.2 V supply showing the effectiveness of the proposed methodology.