Low-power and high-throughput Viterbi decoder (VD) for tail-biting convolutional codes is presented in this paper. First, a low complexity radix-4 architecture is introduced to enable high throughput at low overhead. Second, enhanced decoding features such as end-state forcing and best-state trace back are proposed to improve the decoding performance and their low complexity implementation is also presented. Third, simple predecoding is proposed to decrease the runtime of VD, resulting in significant power saving. The design is implemented in 0.9V TI 45-nm CMOS process at 100 for Long Term Evolution (LTE) as application. More than 90% power saving is achieved with predecoding at a throughput of 120 Mbps and 0.2 dB SNR loss for 10^(-5) frame error rate.