IEEE Workshop on Signal Processing Systems
SiPS 2009

October 7-9 2009
Tampere, Finland

Information for Authors of Accepted Papers

• Stands of 100cm wide by 140cm high will be provided for prints to be displayed in the poster sessions.
• If you need an invitation letter for applying visa to participate IEEE SiPS in Tampere, Finland, send an inquiry email to jarmo.takala@tut.fi.

Accepted Papers

ID	Title
4	A Novel Trace-Pipelined Binary Arithmetic Coder Architecture for JPEG2000
7	Register File Exploration for a Multi-standard Wireless Forward Error Correction ASIP
10	Implementation of the W-CDMA Cell Search on a MPSoC designed for Software Defined Radios
12	Conflict resolution for pipelined layered LDPC Decoders
16	AN ADAPTIVE FAST MULTIPLE REFERENCE FRAME SELECTION ALGORITHM FOR H.264/AVC USING REFERENCE REGION DATA
17	CONSISTENT VIDEO INPAINTING WITH COST-GUIDED MULTIMODAL PHOTOMETRIC CORRECTION
18	ARCHITECTURAL SUPPORT FOR THE ORCHESTRATION OF FINE-GRAINED MULTIPROCESSING FOR PORTABLE STREAMING APPLICATIONS
22	A CHANNEL-ADAPTIVE EARLY TERMINATION STRATEGY FOR LDPC DECODERS
25	TWO-PARALLEL CONCATENATED BCH SUPER-FEC ARCHITECTURE FOR 100-GB/S OPTICAL COMMUNICATIONS
26	SOFTWARE DESIGNS OF IMAGE PROCESSING TASKS WITH INCREMENTAL REFINEMENT OF COMPUTATION
31	LOCALLY ADAPTIVE SPECKLE NOISE REDUCTION USING MAXIMUM A POSTERIORI ESTIMATION BASED ON MAXWELL DISTRIBUTION
32	Memory Access Characteristics of H.264 Video Encoder on Embedded Processor
33	High-speed Area-efficient Versatile Reed-Solomon Decoder Design for Multi-mode Applications
34	Bidirectional Interleavers for LDPC Decoders Using Transmission Gates
36	Low-Complexity Frame-Size Down-Scaling Integrated with IDCT
39	An improved min-sum based column-layered decoding algorithm for LDPC codes
41	IS THE DIFFERENTIAL FREQUENCY-BASED ATTACK (DFA) EFFECTIVE AGAINST RANDOM DELAY INSERTION (RDI)?
43	Approximating Sine Functions using Variable-Precision Taylor Polynomials
45	Reducing Processor Energy Consumption by Compiler Optimization
46	HYBRIDKERNEL: PREEMPTIVE KERNEL WITH EVENT-DRIVEN EXTENSION FOR RESOURCE CONSTRAINED WIRELESS SENSOR NETWORKS
47	LOW-POWER PRE-DECODING BASED VITERBI DECODER FOR TAIL-BITING CONVOLUTIONAL CODES
52	CAC CODEC Designs Based on Numeral Systems
53	SYSTEM LEVEL DSP SYNTHESIS USING VOLTAGE OVERSCALING, UNEQUAL ERROR PROTECTION & ADAPTIVE QUALITY TUNING: APPLICATION TO DCT/IDCT SYSTEM
55	CONFIGURABLE HIGH-PERFORMANCE VIDEO PLATFORM USING MULTIPLE RISC CLUSTERS CONNECTED WITH SEPARATED DATA AND CONTROL NETWORKS
56	HARDWARE REDUCTION METHODOLOGY FOR 2-DIMENSIONAL KURTOTIC FAST ICA BASED ON ALGORITHMIC ANALYSIS AND ARCHITECTURAL SYMMETRY
58	A EARLY BLOCK TYPE DECISION METHOD FOR INTRA PREDICTION IN H.264/AVC
60	Sparse Severe Error Removal in OFDM Demodulators for Erasure Channels
63	Loop Scheduling with Memory Access Reduction under Register Constraints for DSP Applications
65	Interface-based hierarchy for Synchronous Data-Flow Graphs
67	Parallel Object Detection on Heterogeneous Multicore Platforms
69	Robust Tree Construction and Maintenance for Global Time Synchronization Protocols in Wireless Sensor Networks
70	A Novel Circulant Approximation Method for Frequency Domain LMMSE Equalization
71	MULTI-LEVEL MODULATION SOFT-DECISION DEMAPPER FOR DVB-S2
74	A NEW FPGA-BASED POSTPROCESSOR ARCHITECTURE FOR CHANNEL MISMATCH CORRECTION OF TIME INTERLEAVED ADCS
77	Reconfigurable Video Decoder with Transform Acceleration
78	Rectangular Constellation-Based Blind Equalization with Recursive Least-Squares Algorithm
80	DESIGN OF ROTATED QAM MAPPER/DEMAPPER FOR THE DVB-T2 STANDARD
81	SIMD PROCESSOR BASED IMPLEMENTATION OF RECURSIVE FILTERING EQUATIONS
83	Rank Metric Decoder Architectures for Noncoherent Error Control in Random Network Coding
89	Power-aware Evaluation Flow for Digital Decimation Filter Architectures for High-Speed ADCs
96	Morphable DPU: Smart and Efficient Data Path for Signal Processing Applications
97	DESIGN OF AN INTERLAYER DEBLOCKING FILTER ARCHITECTURE FOR H.264/SVC BASED ON A NOVEL SAMPLE-LEVEL FILTERING ORDER
98	FPGA ARCHITECTURE FOR 2D FAST FOURIER TRANSFORM BASED ON 2D DECOMPOSITION FOR LARGE-SIZED DATA
100	Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11n standard
103	AN ULTRA LOW-POWER VAD HARDWARE IMPLEMENTATION FOR INTELLIGENT UBIQUITOUS SENSOR NETWORKS
104	FAST PIPELINE SCHEDULE FOR AN H.264 INTRA FRAME ENCODER WITH EARLY TERMINATION